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Data Sheet
A m p l i fy t h e H u m a n E x p e r i e n c e
(R)
Comlinear CLC1003
features n 1mV max input offset voltage n 0.00005% THD at 1kHz n 5.3nV/Hz input voltage noise >10kHz n -90dB/-85dB HD2/HD3 at 100kHz, RL=100 n <-100dB HD2 and HD3 at 10kHz, RL=1k n Rail-to-Rail input and output n 55MHz unity gain bandwidth n 12V/s slew rate n +80mA, -55mA output current n -40C to +125C operating temperature range n Fully specified at 3V and 5V supplies n CLC1003: Pb-free SOT23-5, SOIC-8 n Future option CLC2003: Dual n Future option CLC4003: Quad applications n Active filters n Sensor interface n High-speed transducer amp n Medical instrumentation n Probe equipment n Test equipment n Smoke detecters n Hand-held analytic instruments
Low Distortion, Low Offset, RRIO Amplifier
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier
General Description
The COMLINEAR CLC1003 is a single channel, high-performance, voltage feedback amplifier with near precision performance, low input voltage noise, and ultra low distortion. The CLC1003 family of amplifiers offers 1mV maximum input offset voltage, 3.5nV/Hz broadband input voltage noise, and 0.00005% THD at 1kHz. These amplifiers also provide 55MHz gain bandwidth product and 12V/s slew rate making them well suited for applications requiring precision DC performance and high AC performance. These COMLINEAR high-performance amplifiers also offer a rail-to-rail input and output, simplifying single supply designs and offering larger dynamic range possibilities. The inputs extend beyond the rails by 500mV. The COMLINEAR CLC1003 family of amplifiers are designed to operate from 2.5V to 12V supplies and operate over the extended temperature range of -40C to +125.
Typical Application - Current Sensing in 3-Phase Motor
VCC
+
CLC1003
-
lph_1
SPM (Smart Power Module)
M
lph_2
Rev 1A
lph_3
Ordering Information
Part Number CLC1003IST5X CLC1003ISO8X* CLC1003ISO8* CLC1003AST5X CLC1003ASO8X* CLC1003ASO8*
*Preliminary Product Information Moisture sensitivity level for all parts is MSL-1. (c)2008 CADEKA Microcircuits LLC www.cadeka.com
Package SOT23-5 SOIC-8 SOIC-8 SOT23-5 SOIC-8 SOIC-8
Pb-Free Yes Yes Yes Yes Yes Yes
RoHS Compliant Yes Yes Yes Yes Yes Yes
Operating Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +125C
Packaging Method Reel Reel Rail Reel Reel Rail
Data Sheet
CLC1003 SOT Pin Configuration
OUT -V S +IN
1 2 3 + 5
CLC1003 SOT23-5 Pin Assignments
Pin No. Pin Name OUT -VS +IN -IN +VS Description Output Negative supply Positive input Negative input Positive supply 1 2 3 4 5
+VS
4
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier
-IN
CLC1003 SOIC Pin Configuration
CLC1003 SOIC Pin Assignments
Pin No. 1 Pin Name NC -IN1 +IN1 -VS NC OUT +VS NC Description No connect Negative input Positive input Negative supply No connect Output Positive supply No connect
NC -IN1 +IN1 -V S
1 2 3 4
8 7 6 5
NC +VS OUT NC
2 3 4 5 6 7 8
CLC2003 Pin Configuration
CLC2003 (Future Option) Pin Configuration
Pin No. Pin Name OUT1 -IN1 +IN1 -VS +IN2 -IN2 OUT2 +VS Description Output, channel 1 Negative input, channel 1 Positive input, channel 1 Negative supply Positive input, channel 2 Negative input, channel 2 Output, channel 2 Positive supply 1 2 3 4 5 6 7 8
OUT1 -IN1 +IN1 -V S
1 2 3 4
8 7 6 5
+VS OUT2 -IN2 +IN2
CLC4003 Pin Configuration
CLC4003 (Future Option) Pin Configuration
Pin No. Pin Name OUT1 -IN1 +IN1 +VS +IN2 -IN2 OUT2 OUT3 -IN3 +IN3 -VS +IN4 -IN4 OUT4 Description Output, channel 1 Negative input, channel 1 Positive input, channel 1 Positive supply Positive input, channel 2 Negative input, channel 2 Output, channel 2 Output, channel 3 Negative input, channel 3 Positive input, channel 3 Negative supply Positive input, channel 4 Negative input, channel 4 Output, channel 4
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Rev 1A
OUT1 -IN1 +IN1 +VS +IN2 -IN2 OUT2
1 2 3 4 5 6 7
14 13 12 11 10 9 8
OUT4 -IN4 +IN4 -VS +IN3 -IN3 OUT3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
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2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the "Absolute Maximum Ratings". The device should not be operated at these "absolute" limits. Adhere to the "Recommended Operating Conditions" for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots.
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier
Parameter Supply Voltage Input Voltage Range
Min 0 -Vs -0.5V
Max 14 +Vs +0.5V
Unit V V
Reliability Information
Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Package Thermal Resistance 5-Lead SOT23 8-Lead SOIC 14-Lead SOIC
Notes: Package thermal resistance (qJA), JDEC standard, multi-layer test boards, still air.
Min -65
Typ
Max 150 150 260
Unit C C C C/W C/W C/W
221 100 88
Recommended Operating Conditions
Parameter Operating Temperature Range (CLC1003I) Operating Temperature Range (CLC1003A) Supply Voltage Range Min -40 -40 2.5 Typ Max +85 +125 12 Unit C C V
Rev 1A
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Data Sheet
Electrical Characteristics at +3V
TA = 25C, Vs = +3V, Rf = 1k, RL = 1k to VS/2, G = 2; unless otherwise noted.
symbol
GBWP UGBW BWSS BWLS tR, tF tS OS SR
parameter
-3dB Gain Bandwidth Product Unity Gain Bandwidth -3dB Bandwidth Large Signal Bandwidth Rise and Fall Time Settling Time to 0.1% Overshoot Slew Rate
conditions
G = 10, VOUT = 0.05Vpp VOUT = 0.05Vpp , Rf = 0 VOUT = 0.05Vpp VOUT = 2Vpp VOUT = 2V step; (10% to 90%) VOUT = 2V step VOUT = 2V step 2V step 2Vpp, 10kHz, RL = 1k 2Vpp, 100kHz, RL = 100 2Vpp, 10kHz, RL = 1k 2Vpp, 100kHz, RL = 100 1Vpp, 1kHz, G=1, RL = 2k > 10kHz > 100kHz
Min
typ
31 50 24 3.3 150 78 0.3 11 -98 -85 -95 -81 0.0005 5.5 3.9 0.088 1.3 -0.340 0.8 0.2
Max
units
MHz
Frequency Domain Response
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier
MHz MHz MHz ns ns % V/s dBc dBc dBc dBc % nV/Hz nV/Hz mV V/C A nA/C nA dB dB mA M pF V dB
Time Domain Response
Distortion/Noise Response
HD2 HD3 THD en 2nd Harmonic Distortion 3rd Harmonic Distortion Total Harmonic Distortion Input Voltage Noise
DC Performance
VIO dVIO Ib dIb Ios PSRR AOL IS RIN CIN CMIR CMRR Input Offset Voltage Average Drift Input Bias Current Average Drift Input Offset Current Power Supply Rejection Ratio Open-Loop Gain Supply Current Input Resistance Input Capacitance Common Mode Input Range Common Mode Rejection Ratio DC , Vcm=0.5V to 2.5V DC VOUT = VS / 2 per channel Non-inverting, G = 1
100 104 1.85 30 1.1 -0.5 to 3.5 94
Input Characteristics
Rev 1A
Output Characteristics
RL = 150 VOUT Output Voltage Swing RL = 1k 0.085 to 2.80 0.04 to 2.91 +75, -40 VOUT = VS / 2 +95, -50 V V mA mA
IOUT ISC
notes:
Output Current Short-Circuit Output Current
1. 100% tested at 25C
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Data Sheet
Electrical Characteristics at 5V
TA = 25C, Vs = 5V, Rf = 1k, RL = 1k to GND, G = 2; unless otherwise noted.
symbol
GBWP UGBW BWSS BWLS tR, tF tS OS SR
parameter
-3dB Gain Bandwidth Product Unity Gain Bandwidth -3dB Bandwidth Large Signal Bandwidth Rise and Fall Time Settling Time to 0.1% Overshoot Slew Rate
conditions
G = 10, VOUT = 0.05Vpp VOUT = 0.05Vpp , Rf = 0 VOUT = 0.05Vpp VOUT = 2Vpp VOUT = 2V step; (10% to 90%) VOUT = 2V step VOUT = 2V step 4V step 2Vpp, 10kHz, RL = 1k 2Vpp, 100kHz, RL = 100 2Vpp, 10kHz, RL = 1k 2Vpp, 100kHz, RL = 100 1Vpp, 1kHz, G=1, RL = 2k > 10kHz > 100kHz
Min
typ
35 55 25 3.6 125 80 0.3 12 -125 -90 -127 -85
0.00005
Max
units
MHz
Frequency Domain Response
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier
MHz MHz MHz ns ns % V/s dBc dBc dBc dBc % nV/Hz nV/Hz 1 2.6 0.7 mV V/C A nA/C A dB dB 2.75 mA M pF V dB
Time Domain Response
Distortion/Noise Response
HD2 HD3 THD en 2nd Harmonic Distortion 3rd Harmonic Distortion Total Harmonic Distortion Input Voltage Noise
5.3 3.5 -1 -2.6 0.050 1.3 -0.30 0.85 0.2
DC Performance
VIO dVIO Ib dIb Ios PSRR AOL IS RIN CIN CMIR CMRR Input Offset Voltage(1) Average Drift Input Bias Current (1) Average Drift Input Offset Current (1) Power Supply Rejection Ratio (1) Open-Loop Gain (1) Supply Current
(1)
DC VOUT = VS / 2 per channel Non-inverting, G = 1
82 95
100 115 2.2 30 1 5.5
Input Characteristics
Input Resistance Input Capacitance Common Mode Input Range Common Mode Rejection Ratio (1) DC , Vcm= -3V to 3V 70
95
Output Characteristics
RL = 150 VOUT Output Voltage Swing RL = 1k (1) -4.7 -4.826 to 4.534 -4.93 to 4.85 +80, -55 VOUT = VS / 2
+115, -90
Rev 1A
V 4.7 V mA mA
IOUT ISC
notes:
Output Current Short-Circuit Output Current
1. 100% tested at 25C
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Data Sheet
Typical Performance Characteristics
TA = 25C, Vs = 5V, Rf = 1k, RL = 1k to GND, G = 2; unless otherwise noted. Non-Inverting Frequency Response
3 G=1 Rf = 0
Inverting Frequency Response
1 0 -1 G = -1 G = -2 G = -5 G = -10
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier
Normalized Gain (dB)
0
Normalized Gain (dB)
G=2 -3 G=5 G = 10 -6 VOUT = 0.05Vpp -9 0.1 1 10 100
-2 -3 -4 -5 -6 -7 0.1 VOUT = 0.05Vpp
1
10
100
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. CL
1 0
Frequency Response vs. CL without RS
4 2
Normalized Gain (dB)
Normalized Gain (dB)
-1 -2 -3 -4 -5 -6 -7 0.1 VOUT = 0.05Vpp
CL = 500pF Rs = 10 CL = 1000pF Rs = 7.5 CL = 3000pF Rs = 4
CL = 500pF 0 -2 -4 -6 -8 CL = 300pF CL = 100pF CL = 50pF VOUT = 0.05Vpp Rs = 0 0.1 1 CL = 10pF
1
10
100
10
100
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. VOUT
3
Frequency Response vs. RL
2 1 RL = 50 RL = 150 RL = 2.5K RL = 1K
Rev 1A
Normalized Gain (dB)
VOUT = 1Vpp -3 VOUT = 2Vpp VOUT = 4Vpp -6
Normalized Gain (dB)
0
0 -1 -2 -3 -4 -5 VOUT = 0.05Vpp
-9 0.1 1 10 100
-6 0.1 1 10 100
Frequency (MHz)
Frequency (MHz)
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Data Sheet
Typical Performance Characteristics
TA = 25C, Vs = 5V, Rf = 1k, RL = 1k to GND, G = 2; unless otherwise noted. Non-Inverting Frequency Response at VS = 3V
3 G=1 Rf = 0
Inverting Frequency Response at VS = 3V
1 0 -1 G = -1 G = -2 G = -5 G = -10
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier
Normalized Gain (dB)
0
Normalized Gain (dB)
G=2 -3 G=5 G = 10 -6 VOUT = 0.05Vpp -9 0.1 1 10 100
-2 -3 -4 -5 -6 -7 0.1 VOUT = 0.05Vpp
1
10
100
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. VOUT at VS = 3V
3
Frequency Response vs. RL at VS = 3V
2 1 RL = 50 RL = 150 RL = 2.5K RL = 1K
Normalized Gain (dB)
VOUT = 1Vpp -3 VOUT = 2Vpp VOUT = 2.5Vpp -6
Normalized Gain (dB)
0
0 -1 -2 -3 -4 -5 VOUT = 0.05Vpp
-9 0.1 1 10 100
-6 0.1 1 10 100
Frequency (MHz)
Frequency (MHz)
-3dB Bandwidth vs. Output Voltage at VS = 3V
24 21
-3dB Bandwidth vs. Output Voltage
24 21
Rev 1A
-3dB Bandwidth (MHz)
-3dB Bandwidth (MHz)
0.0 0.5 1.0 1.5 2.0 2.5
18 15 12 9 6 3 0
18 15 12 9 6 3 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VOUT (VPP)
VOUT (VPP)
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Data Sheet
Typical Performance Characteristics - Continued
TA = 25C, Vs = 5V, Rf = 1k, RL = 1k to GND, G = 2; unless otherwise noted. Open Loop Gain and Phase vs. Frequency
80 60 40 0 -75 -150
CMIR
0.5 0.4 0.3
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier
PHASE
GAIN (dB)
PHASE ()
GAIN
Vout (V)
20 0 -20 -40 -60 10 100
-225 -300 -375 -450 -525
0.2 0.1 0 -0.1 -6 -4 -2 0 2 4 6
1,000
10,000
100,000
1,000,000
FREQ (KHz)
Vni(V)
Input Voltage Noise
14 13 12 11 10 8 7 6 5 4 3 2 0.0001 0.001 0.01 0.1 1
CMIR at VS = 3V
0.5 0.4 0.3
Input Voltage Noise (nV/Hz)
Vout (V)
9
0.2 0.1 0 -0.1 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4
Frequency (MHz)
Vni(V)
CMRR vs. Frequency
110 100 90
PSRR vs. Frequency
110 100 90
Rev 1A
CMRR (dB)
80 70 60 50 40 0.001 0.01 0.1 1 10 100 1000
CMRR (dB)
80 70 60 50 40 0.001 0.01 0.1 1 10 100 1000
Frequency (MHz)
Frequency (MHz)
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Data Sheet
Typical Performance Characteristics - Continued
TA = 25C, Vs = 5V, Rf = 1k, RL = 1k to GND, G = 2; unless otherwise noted. 2nd Harmonic Distortion vs. RL
-50 -60 -70 -80 -90 RL = 500 -100 VOUT = 2Vpp -110 100 200 300 400 500 600 700 800 900 1000 -110 100 200 300 400 500 600 700 800 900 1000 -100 VOUT = 2Vpp RL = 10K
3rd Harmonic Distortion vs. RL
-50 -60 RL = 10K -70 -80 -90 RL = 500 RL = 1K
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier
RL = 100
Distortion (dBc)
Distortion (dBc)
RL = 100
RL = 1K
Frequency (KHz)
Frequency (KHz)
2nd Harmonic Distortion vs. VOUT
-40 -50 -60 -70 -80 RF=RL=10K -90 FREQ = 500KHz -100 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5
3rd Harmonic Distortion vs. VOUT
-30 -40 -50
Distortion (dBc)
RF=RL=1K
Distortion (dBc)
-60 -70 -80
RF=RL=1K
RF=RL=10K -90 -100 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 FREQ = 500KHz
Output Amplitude (Vpp)
Output Amplitude (Vpp)
THD vs. Frequency
-65 -70 -75
Rev 1A
THD (dB)
-80 -85 -90 -95 -100 100 200 300 400 500 600 700 800 900 1000 VOUT = 1Vpp RL = 1K AV+1
Frequency (kHz)
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Data Sheet
Typical Performance Characteristics - Continued
TA = 25C, Vs = 5V, Rf = 1k, RL = 1k to GND, G = 2; unless otherwise noted. 2nd Harmonic Distortion vs. RL at VS = 3V
-40 -50 -60 -70 -80 -90 VOUT = 2Vpp -100 100 200 300 400 500 600 700 800 900 1000 -100 100 200 300 400 500 600 700 800 900 1000 RL = 500 RL = 1K RL = 100
3rd Harmonic Distortion vs. RL at VS = 3V
-40 -50 -60 RL = 100 -70 -80 RL = 500 -90 VOUT = 2Vpp
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier
Distortion (dBc)
RL = 10K
Distortion (dBc)
RL = 1K
RL = 10K
Frequency (KHz)
Frequency (KHz)
2nd Harmonic Distortion vs. VOUT at VS = 3V
-40 -50 -60 RF=RL=10K -70 -80 -90 FREQ = 500KHz -100 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
3rd Harmonic Distortion vs. VOUT at VS = 3V
-40 -50 -60 RF=RL=10K -70 -80 -90 FREQ = 500KHz -100 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
Distortion (dBc)
RF=RL=1K
Distortion (dBc)
RF=RL=1K
Output Amplitude (Vpp)
Output Amplitude (Vpp)
THD vs. Frequency at VS = 3V
-65 -70 -75
Rev 1A
THD (dB)
-80 -85 -90 -95 -100 100 200 300 400 500 600 700 800 900 1000 VOUT = 1Vpp RL = 1K AV+1
Frequency (kHz)
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Data Sheet
Typical Performance Characteristics - Continued
TA = 25C, Vs = 5V, Rf = 1k, RL = 1k to GND, G = 2; unless otherwise noted. Small Signal Pulse Response
0.75 0.5 0.25
Small Signal Pulse Response at VS = 3V
1.65 1.6 1.55
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier
Voltage (V)
0 -0.25 -0.5 -0.75 0 0.5 1 1.5 2
Voltage (V)
1.5 1.45 1.4 1.35 0 0.5 1 1.5 2
Time (ns)
Time (ns)
Large Signal Pulse Response
6 4 2
Large Signal Pulse Response at VS = 3V
3 2.5 2
Voltage (V)
0 -2 -4 -6 0 1 2 3 4 5 6 7 8 9 10
Voltage (V)
1.5 1 0.5 0 0 0.5 1 1.5 2
Time (ns)
Time (ns)
Input Offset Voltage vs. Temperature
0.1 0.05 0
Input Offset Voltage Distribution
5000
Rev 1A
4000
3000
Vio (V)
-0.05 -0.1
Units
2000 1000 0
-0.15 -0.2 -40 -20 0 20 40 60 80 100 120
0.14
0.42
-0.98
-0.42
Temperature (C)
Input Offset Voltage (mV)
-0.14
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0.98
-0.7
0.7
11
Data Sheet
Application Information
Basic Operation Figures 1 and 2 illustrate typical circuit configurations for non-inverting, inverting, and unity gain topologies for dual supply applications. They show the recommended bypass capacitor values and overall closed loop gain equations.
+Vs 6.8F
perature, the package thermal resistance value ThetaJA (JA) is used along with the total die power dissipation. TJunction = TAmbient + (JA x PD) Where TAmbient is the temperature of the working environment. In order to determine PD, the power dissipated in the load needs to be subtracted from the total power delivered by the supplies. PD = Psupply - Pload Supply power is calculated by the standard power equation.
Output
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier
Input
+ -
0.1F
Psupply = Vsupply x IRMS supply Vsupply = VS+ - VSPower delivered to a purely resistive load is: Pload = ((VLOAD)RMS2)/Rloadeff The effective load resistor (Rloadeff) will need to include the effect of the feedback network. For instance, Rloadeff in figure 3 would be calculated as:
0.1F Rg -Vs 6.8F
RL Rf
G = 1 + (Rf/Rg)
Figure 1. Typical Non-Inverting Gain Circuit
+Vs 6.8F
RL || (Rf + Rg) These measurements are basic and are relatively easy to perform with standard lab equipment. For design purposes however, prior knowledge of actual signal levels and load impedance is needed to determine the dissipated power. Here, PD can be found from PD = PQuiescent + PDynamic - PLoad
G = - (Rf/Rg) For optimum input offset voltage set R1 = Rf || Rg
R1 Input Rg
+ -
0.1F Output 0.1F 6.8F -Vs RL Rf
Figure 2. Typical Inverting Gain Circuit
Quiescent power can be derived from the specified IS values along with known supply voltage, VSupply. Load power can be calculated as above with the desired signal amplitudes using: (VLOAD)RMS = VPEAK / 2 ( ILOAD)RMS = ( VLOAD)RMS / Rloadeff The dynamic power is focused primarily within the output stage driving the load. This value can be calculated as: PDYNAMIC = (VS+ - VLOAD)RMS x ( ILOAD)RMS Assuming the load is referenced in the middle of the power rails or Vsupply/2. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the packages available.
Rev 1A
Power Dissipation Power dissipation should not be a factor when operating under the stated 300 ohm load condition. However, applications with low impedance, DC coupled loads should be analyzed to ensure that maximum allowed junction temperature is not exceeded. Guidelines listed below can be used to verify that the particular application will not cause the device to operate beyond it's intended operating range. Maximum power levels are set by the absolute maximum junction rating of 150C. To calculate the junction tem-
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Data Sheet
2.5
Maximum Power Dissipation (W)
2
SOIC-8
For a given load capacitance, adjust RS to optimize the tradeoff between settling time and bandwidth. In general, reducing RS will increase bandwidth at the expense of additional overshoot and ringing. Overdrive Recovery
1.5
SOT23-6
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier
1
0.5
0 -40 -20 0 20 40 60 80
Ambient Temperature (C)
Figure 3. Maximum Power Derating
An overdrive condition is defined as the point when either one of the inputs or the output exceed their specified voltage range. Overdrive recovery is the time needed for the amplifier to return to its normal or linear operating point. The recovery time varies, based on whether the input or output is overdriven and by how much the range is exceeded. The CLCx003 will typically recover in less than 20ns from an overdrive condition. Figure 5 shows the CLC1003 in an overdriven condition.
3 2 VIN = .8Vpp G=5 2 2 1
Driving Capacitive Loads Increased phase delay at the output due to capacitive loading can cause ringing, peaking in the frequency response, and possible unstable behavior. Use a series resistance, RS, between the amplifier and the load to help improve stability and settling performance. Refer to Figure 4.
Input + Rf Rg Rs CL RL
Output Voltage (V)
Input Voltage (V)
1 0
Input
1 0 Output -1 -1
-1 -2 -3 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
Output
-2 -2
Time (us)
Figure 5. Overdrive Recovery Figure 4. Addition of RS for Driving Capacitive Loads The CLC1003 family of amplifiers is capable of driving up to 300pF directly, with no series resistance. Directly driving 500pF causes over 4dB of frequency peaking, as shown in the plot on page 6. Table 1 provides the recommended RS for various capacitive loads. The recommended RS values result in <=1dB peaking in the frequency response. The Frequency Response vs. CL plots, on page 6, illustrates the response of the CLCx003.
CL (pF) 500 1000 3000 RS () 10 7.5 4 -3dB BW (MHz) 27 20 15
IN Rt
Considerations for Offset and Noise Performance Offset Analysis There are three sources of offset contribution to consider; input bias current, input bias current mismatch, and input offset voltage. The input bias currents are assumed to be equal with and additional offset current in one of the inputs to account for mismatch. The bias currents will not affect the offset as long as the parallel combination of Rf and Rg matches Rt. Refer to Figure 6.
Rg Rf +Vs
Rev 1A
- +
CLC1003
RL
Table 1: Recommended RS vs. CL
-Vs
Figure 6: Circuit for Evaluating Offset
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Data Sheet
The first place to start is to determine the source resistance. If it is very small an additional resistance may need to be added to keep the values of Rf and Rg to practical levels. For this analysis we assume that Rt is the total resistance present on the non-inverting input. This gives us one equation that we must solve: Rt = Rg||Rf This equation can be rearranged to solve for Rg: Rg = (Rt * Rf) / (Rf - Rt) The other consideration is desired gain (G) which is: G = (1 + Rf/Rg) By plugging in the value for Rg we get Rf = G * Rt And Rg can be written in terms of Rt and G as follows: Rg = (G * Rt) / (G - 1) The complete input offset equation is now only dependent on the voltage offset and input offset terms given by: VI OS =
Where Vorext is the noise due to the external resistors and is given by:
2 v o
= en 1 +
RF RG
2
+ eG
RF RG
2
+ eF
2
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier
The complete equation can be simplified to:
2 v o
= 3 4kT G RT + enG
(
)( )
2
+ 2 in RT
(
)
2
It's easy to see that the effect of amplifier voltage noise is proportionate to gain and will tend to dominate at large gains. The other terms will have their greatest impact at large Rt values at lower gains.
Layout Considerations General layout and supply bypassing play major roles in high frequency performance. CADEKA has evaluation boards to use as a guide for high frequency layout and as aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: * Include 6.8F and 0.1F ceramic capacitors for power supply decoupling * Place the 6.8F capacitor within 0.75 inches of the power pin * Place the 0.1F capacitor within 0.1 inches of the power pin * Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance * Minimize all trace lengths to reduce series inductances
( VIO ) + (IOS RT)
2
2
2
And the output offset is: VO OS = G Noise analysis The complete equivalent noise circuit is shown in Figure 7.
Rg
+-
( V IO ) + (I OS RT )
2
Rf
+-
Rev 1A
- Rg
+- + - +-
+
CLC1003
RL
Refer to the evaluation board layouts below for more information.
Figure 7: Complete Equivalent Noise Circuit The complete noise equation is given by:
2 v o 2 RF = vorext + en 1 + RG 2
(c)2004-2008 CADEKA Microcircuits LLC
w
Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of these devices: Evaluation Board #
2
Products CLC1003 in SOT23-5 CLC1003 in SOIC-8
+ ibp RT 1 +
RF RG
+ ibn RF
(
)
2
CEB002 CEB003
www.cadeka.com
14
Data Sheet
Evaluation Board Schematics Evaluation board schematics and layouts are shown in Figures 8-13. These evaluation boards are built for dual- supply operation. Follow these steps to use the board in a single-supply application: 1. Short -Vs to ground. 2. Use C3 and C4, if the -VS pin of the amplifier is not directly connected to the ground plane.
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier
Figure 10. CEB002 Bottom View
Figure 8. CEB002 Schematic
Figure 11. CEB003 Top View
Rev 1A
Figure 9. CEB002 Top View
Figure 12. CEB003 Bottom View
www.cadeka.com
(c)2004-2008 CADEKA Microcircuits LLC
15
Data Sheet
Mechanical Dimensions
SOT23-5 Package
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier
SOIC-8
Rev 1A
For additional information regarding our products, please visit CADEKA at: cadeka.com
caDeKa Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5415 (toll free)
CADEKA, the CADEKA logo design, and Comlinear and the Comlinear logo design, are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright (c)2008 by CADEKA Microcircuits LLC. All rights reserved.
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